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general description the max1739/max1839 fully integrated controllers are optimized to drive cold-cathode fluorescent lamps (ccfls) using the industry-proven royer oscillator inverter architecture. the royer architecture provides near sinusoidal drive waveforms over the entire input range to maximize the life of ccfls. the max1739/ max1839 optimize this architecture to work over a wide input voltage range, achieve high efficiency, and maxi- mize the dimming range. the max1739/max1839 monitor and limit the trans- former center-tap voltage when required. this ensures minimal voltage stress on the transformer, which increases the operating life of the transformer and eases its design requirements. these controllers also provide protection against many other fault conditions, including lamp-out and buck short faults. these controllers achieve 50:1 dimming range by simultaneously adjusting lamp current and ?hopping the ccfl on and off using a digitally adjusted pulse- width modulated (dpwm) method. ccfl brightness is controlled by an analog voltage or is set with an smbus tm -compatible two-wire interface (max1739). the max1739/max1839 drive an external high-side n-channel power mosfet and two low-side n-channel power mosfets, all synchronized to the royer oscilla- tor. an internal 5.3v linear regulator powers the mos- fet drivers and most of the internal circuitry. the max1739/max1839 are available in space-saving 20-pin qsop packages and operate over the -40? to +85? temperature range. ________________________applications notebook/laptop computers car navigation displays lcd monitors point-of-sale terminals portable display electronics features fast response to input change wide input voltage range (4.6v to 28v) high power-to-light efficiency minimizes transformer voltage stress lamp-out protection with 2s timeout buck switch short and other single-point fault protection integrated royer mosfet drivers reduce transformer pin count buck operation synchronized to royer oscillator synchronizable dpwm frequency pin-selectable brightness control interface smbus serial interface (max1739) analog interface (max1739/max1839) max1739/max1839 ? wide brightness range ccfl backlight controllers ________________________________________________________________ maxim integrated products 1 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 batt dh lx bst ccv cci mindac ref top view vl gnd cs dl1 mode ctl/scl crf/sda sh/sus 12 11 9 10 dl2 sync ctfb csav max1739 qsop pin configuration 19-1755; rev 1; 3/01 for price, delivery, and to place orders, please contact maxim distribution at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. ? patent pending smbus is a trademark of intel corp. part temp. range pin-package max1739 eep -40 c to +85 c 20 qsop max1839 eep -40 c to +85 c 20 qsop ordering information pin configurations continued at end of data sheet.
max1739/max1839 ? wide brightness range ccfl backlight controllers 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v+ = 8.2v, v sh /sus = v sh = 5.5v, mindac = gnd, t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25 c.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v batt to gnd ...........................................................-0.3v to 30v v bst , v sync to gnd.................................................-0.3v to 34v v bst to v lx .................................................................-0.3v to 6v v dh to v lx .................................................-0.3v to (v bst + 0.3v) v lx to gnd...................................................-6v to (v bst + 0.3v) vl to gnd...................................................................-0.3v to 6v v ccv , v cci , v ref , v dl1 , v dl2 to gnd .........-0.3v to (vl + 0.3v) v mindac , v ctfb , v csav to gnd ................................-0.3v to 6v v cs to gnd...................................................-0.6v to (vl + 0.3v) v mode to gnd.............................................................-6v to 12v v crf/sda , v crf , v ctl/scl , v ctl , v sh /sus , v sh to gnd ............................................................-0.3v to 6v continuous power dissipation (t a = +70 c) 20-pin qsop (derate 9.1mw/ c above +70 c)...........727mw operating temperature .......................................-40 c to +85 c storage temperature.........................................-65 c to +150 c lead temperature (soldering, 10s) .................................+300 c parameter conditions min typ max units supply and reference v l = v batt 4.6 5.5 v batt input voltage range v l = open 6 28 v v batt = 28v 3.2 6 v batt quiescent current, operation with full duty cycle on dh dh = dl1 = dl2 = open v batt = v l = 5v 3.2 6 ma v batt quiescent current, shutdown sh /sus = sh = gnd 6 20 a vl output voltage, normal operation 6v < v batt < 28v, 0 < i load < 15ma 5.0 5.35 5.5 v vl output voltage, shutdown sh /sus = sh = gnd, no load 3.5 4.5 5.5 v vl rising (leaving lockout) 4.6 vl undervoltage lockout threshold vl falling (entering lockout) 4.0 v vl undervoltage lockout hysteresis 300 mv ref output voltage, normal operation 4.5v < vl < 5.5v, i ref = 40 a 1.96 2.00 2.04 v v l por threshold 0.9 2.7 v switching regulator dh driver on-resistance 18 ? dl1, dl2 driver on-resistance 18 ? minimum dh switching frequency 1/t dh , sync = cs or gnd, not synchronized 49 56 64 khz dh minimum off-time 250 375 500 ns dh maximum duty cycle 98 % sync synchronization range detect falling edges on sync 64 200 khz sync input current 0 < v sync < 30v -2 2 a sync input threshold sync falling, referred to cs 400 500 600 mv sync input hysteresis referred to the sync input threshold 50 100 150 mv sync threshold crossing to dl1, dl2 toggle delay v sync = 0 to 5v, c dl_1 and c dl_2 < 100pf, 50% point on sync to 50% point on dl1 or dl2 120 ns cs overcurrent threshold 408 450 492 mv
max1739/max1839 ? wide brightness range ccfl backlight controllers _______________________________________________________________________________________ 3 electrical characteristics (continued) (v+ = 8.2v, v sh /sus = v sh = 5.5v, mindac = gnd, t a = 0 c to +85 c , unless otherwise noted. typical values are at t a = +25 c.) parameter conditions min typ max units dac and error amplifier dac resolution guaranteed monotonic 5 bits mindac input voltage range 0 2 v mindac input bias current 0 < v mindac < 2v -1 1 a mindac digital pwm disable threshold mindac = vl 2.4 2.9 4 v csav input voltage range 0 0.8 v v mindac = 0, dac code = 11111 binary 188 194 200 v mindac = 0, dac code = 00001 binary 2 6.25 16 csav regulation point v mindac = 1v, dac code = 00000 binary 93 100 110 mv csav input bias current -1 1 a csav to cci transconductance 1v < v cci < 2.7v 100 mho ctfb input voltage range 0 2 v ctfb input bias current -1 1 a ctfb regulation point 570 600 630 mv ctfb to ccv transconductance 1v < v ccv < 2.7v 30 40 50 mho timers and fault detection chopping oscillator frequency no ac signal on mode, not synchronized 24 28 32 khz no ac signal on mode 205 220 235 32khz ac signal on mode 250 digital pwm chop-mode frequency 100khz ac signal on mode 781 hz mode to dpwm sync ratio f mode / f dpwm 128 no ac signal on mode 2.06 2.33 2.73 32khz ac signal on mode 2.05 lamp-out detection timeout timer (center-tap voltage stuck at maximum) (note 1) v csav < csav lamp-out threshold 100khz ac signal on mode 0.66 s csav lamp-out threshold 50 75 100 mv fault-detection threshold on ccv (note 2) 0.4 1 v no ac signal on mode 332 291 259 32khz ac signal on mode 256 shorted buck-switch detection timeout timer (ul1950 protection) (note 3) v ccv < fault- detection threshold on ccv 100khz ac signal on mode 82 ms lamp turn-on delay after sh /sus or sh forces device on or sh rises 4 ms mode operating voltage range -5.5 11 v mode = gnd threshold (min brightness = 0) to sync dpwm oscillator, not in shutdown (note 4) 0.6 v mode = ref threshold (max brightness = 0) to sync dpwm oscillator, not in shutdown (note 4) 1.4 2.6 v mode = v l threshold (max1739 smb interface mode) to sync dpwm oscillator, not in shutdown (note 4) vl - 0.6 v mode ac signal amplitude peak to peak (note 5) 2 v mode ac signal synchronization range chopping oscillator synchronized to mode ac signal 32 100 khz
max1739/max1839 ? wide brightness range ccfl backlight controllers 4 _______________________________________________________________________________________ electrical characteristics (continued) (v+ = 8.2v, v sh /sus = v sh = 5.5v, mindac = gnd, t a = 0 c to +85 c , unless otherwise noted. typical values are at t a = +25 c.) parameter conditions min typ max unit analog interface brightness control (mode connected to ref or gnd ) crf/sda, crf input range 2.7 5.5 v v crf/sda = v crf = 5.5v 20 a crf/sda, crf input current v crf/sda = v crf = 5.5v, sh /sus = sh = 0 -1 1 a ctl/scl, input range max1739 0 crf/ sda v ctl input range max1839 0 crf v ctl/scl, ctl input current mode = ref or gnd -1 1 a adc resolution guaranteed monotonic 5 bits adc hysteresis 1 lsb sh input low voltage 0.8 v sh input high voltage 2.1 v sh /sus input hysteresis when transitioning in and out of shutdown 150 mv sh input bias current -1 1 a system management bus brightness control (max1739, mode connected to v l , see figures 12 and 13) crf/sda, ctl/scl, sh /sus input 0.8 v crf/sda, ctl/scl, sh /sus input 2.1 v crfsda, ctlscl input hysteresis 300 mv crf/sda, ctl/scl, sh /sus input -1 1 a crf/sda output low sink current v crf/sda = 0.4v 4 ma ctl/scl serial clock high period t high 4s ctl/scl serial clock low period t low 4.7 s start condition setup time t su:sta 4.7 s start condition hold time t hd:sta 4s c rf/s d a v al id to c tl/s c l ri si ng e d g e s etup ti m e, s l ave c l ocki ng i n d ata t su:dat 250 ns ctl/scl falling edge to crf/sda transition t hd:dat 0ns ctl/scl falling edge to crf/sda valid, reading out data t dv 1s
max1739/max1839 ? wide brightness range ccfl backlight controllers _______________________________________________________________________________________ 5 electrical characteristics (v+ = 8.2v, v sh /sus = v sh = 5.5v, mindac = gnd, t a = -40 c to +85 c , unless otherwise noted.) (note 6) parameter conditions min typ max units supply and reference vl = v batt 4.6 5.5 v batt input voltage range vl = open 6 28 v v batt quiescent current, shutdown sh /sus = sh = gnd 20 a vl output voltage, normal operation 6v < v batt < 28v, 0 < i load < 15ma 5.0 5.6 v vl rising (leaving lockout) 4.6 vl undervoltage lockout threshold vl falling (entering lockout) 4.0 v ref output voltage, normal operation 4.5v < vl < 5.5v, i ref = 40a 1.95 2.05 v vl por threshold 0.9 2.7 v switching regulator dh driver on-resistance 18 ? dl1, dl2 driver on-resistance 18 ? sync synchronization range detect falling edges on sync 64 200 khz cs overcurrent threshold 408 492 mv dac and error amplifier csav regulation point v mindac = 0, dac code = 11111 binary 186 202 mv ctfb regulation point 560 640 mv ctfb to ccv transconductance 1v < v ccv < 2.7v 30 50 mho analog interface brightness control (mode connected to ref or mode connected to gnd) sh input low voltage 0.8 v sh input high voltage 2.1 v system management bus brightness control (mode connected to vl) crf/sda, ctl/scl, sh /sus input low voltage 0.8 v crf/sda, ctl/scl, sh /sus input high voltage 2.1 v crf/sda output low sink current v crf/sda = 0.4v 4 ma note 1: corresponds to 512 dpwm cycles or 65536 mode cycles. note 2: when the buck switch is shorted, v ctfb goes high causing v ccv to go below the fault detection threshold. note 3: corresponds to 64 dpwm cycles or 8192 mode cycles. note 4: the mode pin thresholds are only valid while the part is operating. in shutdown, v ref = 0 and the part only differentiates between smb mode and adc mode. in shutdown with adc mode selected, the crf/sda and ctl/scl pins are at high impedance and will not cause extra supply current when their voltages are not at gnd or vl. v amplitude > 2v mode 500pf 10k note 5: the amplitude is measured with the following circuit: note 6: specifications from -40 c to +85 c are guaranteed by design, not production tested.
max1739/max1839 ? wide brightness range ccfl backlight controllers 6 _______________________________________________________________________________________ typical operating characteristics (v in = 12v, v ctl = v crf , v mindac = 1v, mode = gnd, circuit of figure 8.) 4 s/div wide input range (v batt = 8v) v csav 500mv/div v ctap 5v/div v dh 20v/div max1739/1839 toc01 4 s/div wide input range (v batt = 20v) v csav 500mv/div v ctap 5v/div v dh 20v/div max1739/1839 toc02 100 s/div v cci v cci v cci v ccv v ccv v ccv wide input range (v batt = 8v, dpwm = 9%, v ctl = 0) v csav 500mv/div v ctap 10v/div v ccv, v cci 200mv/div 1.2v max1739/1839 toc03 100 s/div v cci v cci v cci v ccv v ccv v ccv wide input range (v batt = 20v, dpwm = 9%, v ctl = 0) v csav 500mv/div v ctap 10v/div v ccv , v cci 200mv/div 1.2v max1739/1839 toc04 20 s/div feed-forward compensation v ctap 5mv/div v in 20v 10v v csav 500mv/div v dh 20v/div max1739/1839 toc05 4 s/div switching waveforms v csav 500mv/div v ctap 10v/div v dh 20v/div v dl 5v/div max1739/1839 toc08
max1739/max1839 ? wide brightness range ccfl backlight controllers _______________________________________________________________________________________ 7 typical operating characteristics (continued) (v in = 12v, v ctl = v crf , v mindac = 1v, mode = gnd, circuit of figure 8.) 20ms/div startup (adc soft-start, mode = gnd) v ctap 10v/div v batt v csav 500mv/div i batt 500ma/div max1739/1839 toc09 12v 0 2ms/div lamp-out voltage limiting v secondary 2kv/div v ctap 5v/div max1739/1839 toc10 1ms/div synchronized dpwm (f mode = 100khz, v ctl = v crf /2) v csav 500mv/div v ctap 5v/div v dh 20v/div max1739/1839 toc07 1ms/div synchronized dpwm (f mode = 32khz, v ctl = v crf /2) v csav 500mv/div v ctap 5v/div v dh 20v/div max1739/1839 toc06 400ms/div lamp-out voltage limiting v secondary 2kv/div v ctap 5v/div max1739/1839 toc11 0 200 100 500 400 300 800 700 600 900 010 5 152025 input current vs. input voltage max1739/1839 toc12 v batt (v) i batt (ma) 0 2 1 5 4 3 8 7 6 9 shutdown current ( a) shutdown minimum brightness maximum brightness
max1739/max1839 ? wide brightness range ccfl backlight controllers 8 _______________________________________________________________________________________ 5.40 5.10 0.01 1 10 0.1 100 vl vs. i vl max1739/1839 toc13 i vl (ma) vl (v) shutdown vl (v) 5.15 5.20 5.25 5.30 5.35 4.6 4.0 4.1 4.2 4.3 4.4 4.5 shutdown normal operation 6 0 01015 525 20 vl vs. batt voltage max1739/1839 toc14 v batt (v) vl (v) 1 2 3 4 5 normal operation shutdown 5.31 5.32 5.34 5.33 5.35 5.36 -40 10 -15 356085 vl vs. temperature max1739/1839 toc15 temperature ( c) vl (v) 4.35 4.40 4.50 4.45 4.55 4.60 shutdown vl (v) shutdown normal operation typical operating characteristics (continued) (v in = 12v, v ctl = v crf , v mindac = 1v, mode = gnd, circuit of figure 8.)
max1739/max1839 ? wide brightness range ccfl backlight controllers _______________________________________________________________________________________ 9 _______________________________________________________________________________________ name pin max1739 max1839 function 1 ref ref 2v reference output. bypass to gnd with 0.1 f. forced low during shutdown. 2 mindac mindac dac zero-scale input. v mindac sets the dac s minimum scale output voltage. disable dpwm by connecting mindac to vl. 3 cci cci gmi output. output of the current loop gmi amplifier that regulates the ccfl current. typically bypass to gnd with 0.1 f . 4 ccv ccv gmv output. output of the voltage loop gmv amplifier that regulates the maximum average primary transformer voltage. typically bypass to gnd with 3300p f . 5 sh /sus sh logic low shutdown input in analog interface mode. smbus suspends input in smbus interface mode (max1739 only). 6 crf/sda crf 5- bi t ad c reference input in anal og inter face mod e. bypass to gn d wi th 0.1 f. sm bus seri al d ata i np ut/op en- d r ai n outp ut ( max 1739 onl y) i n s m bus i nter face m od e. 7 ctl/scl ctl ccfl brightness control input in analog interface mode. smbus serial clock input (max1739 only) in smbus interface mode. 8 mode mode interface selection input and sync input for dpwm chopping (see synchronizing the dpwm frequency ). the average voltage on the mode pin selects one of three ccfl brightness control interfaces: 1) mode = vl, enables smbus serial interface (max1739 only). 2) mode = gnd, enables the analog interface (positive scale analog interface mode); v ctl/scl = 0 means minimum brightness. 3) mode = ref, enables the analog interface (negative scale analog interface mode); v ctl/scl = 0 means maximum brightness. 9 csav csav current-sense input. input to the gmi error amplifier that drives cci. 10 ctfb ctfb center-tap voltage feedback input. the average v ctfb is limited to 0.6v. 11 sync sync royer synchronization input. falling edges on sync force dh on and toggle the dl1 and dl2 drivers. connect directly to the royer center tap. 12 dl2 dl2 low-side n-channel mosfet 2 gate drive. drives the royer oscillator switch. dl1 and dl2 have make-before-break switching, where at least one is always on. falling edges on sync toggle dl1 and dl2 and turn dh on. 13 dl1 dl1 low-side n-channel mosfet 1 gate drive 14 cs cs current-sense input (current limit). the current-mode regulator terminates the switch cycle when v cs exceeds (v ref - v cci ). 15 gnd gnd system ground 16 vl vl 5.3v linear regulator output. supply voltage for most of the internal circuits. bypass with 1 f capacitor to gnd. can be connected to v batt if v batt < 5.5v. 17 bst bst high-side driver bootstrap input. connect through a diode to vl and bypass with 0.1 f capacitor to lx. 18 lx lx high-side driver ground input 19 dh dh high-side gate driver output. falling edges on sync turn on dh. 20 batt batt supply input. input to the internal 5.3v linear regulator that powers the chip. pin description
max1739/max1839 ? wide brightness range ccfl backlight controllers 10 ______________________________________________________________________________________ detailed description the max1739/max1839 regulate the brightness of a ccfl in three ways: 1) linearly controlling the lamp current. 2) digitally pulse-width modulating (or chopping) the lamp current (dpwm). 3) using both methods simultaneously for widest dim- ming range. dpwm is implemented by pulse-width modulating the lamp current at a rate faster than the human eye can detect. figure 1 shows the current and voltage wave- forms for the three operating modes with the brightness control set to 50% of full scale. the max1739/max1839 include a 5.3v linear regulator to power most of the internal circuitry, drivers for the buck and royer switches, and the synchronizable dpwm oscillator. the max1739/max1839 are very flex- ible and include a variety of operating modes, an ana- log interface, an smbus interface (max1739 only), a shutdown mode, lamp-out detection, and buck-switch short detection. figure 1. brightness control methods v mindac = 0 v ctl = v crf /2 or bright[4:0] = 10,000 (dac set to midscale) effective brightness is: 50% in continuous and dpwm control 25% in combined control v ctap v csav current + dpwm control continuous current control dpwm control v ctap transformer voltage v csav lamp current
max1739/max1839 ? wide brightness range ccfl backlight controllers _______________________________________________________________________________________ 11 voltage and current control loops the max1739/max1839 use two control loops. the cur- rent control loop regulates the average lamp current. the voltage control loop limits the maximum average primary- side transformer voltage. the voltage control loop is active during the beginning of dpwm on-cycles and in some fault conditions. limiting the transformer primary voltage allows for a lower transformer secondary voltage rating that can increase reliability and decrease cost of the transformer. the voltage control loop acts to limit the transformer voltage any time the current control loop attempts to steer the transformer voltage above its limit as set by v ctfb (see sense resistors ). the voltage control loop uses a transconductance amplifier to create an error current based on the volt- age between ctfb and the internal reference level (600mv typ) (figure 2). the error current is then used to charge and discharge c ccv to create an error volt- age v ccv . the current control loop produces a similar signal based on the voltage between csav and its internal reference level (see the dimming range sec- tion). this error voltage is called v cci . the lower of v ccv and v cci is used with the buck regulator s pwm ramp generator to set the buck regulator s duty cycle. during dpwm, the two control loops work together to limit the transformer voltage and to allow wide dimming range with good line rejection. during the dpwm off- cycle, v ccv is set to 1.2v and cci is set to high imped- ance. v ccv is set to 1.2v to create soft-start at the beginning of each dpwm on-cycle in order to avoid overshoot on the transformer primary. v cci is set to high impedance to keep v cci from changing during the off-cycles. this allows the current control loop to regu- late the average lamp current only during dpwm on- cycles and not the overall average lamp current. upon power-up, v cci slowly rises, increasing the duty cycle, which provides soft-start. during this time, v ccv , which is the faster control loop, is limited to 150mv above v cci by the ccv-clamp . once the secondary voltage reaches the strike voltage, the lamp current begins to increase. when the lamp current reaches the regulation point, v cci reaches steady state. with min- dac = vl (dpwm disabled), the current control loop remains in control and regulates the lamp current. with mindac between ref and gnd, dpwm is enabled and the max1739/max1839 begin pulsing the lamp current. during the on-cycle, v ccv is at 150mv above v cci . after the on-cycle, v ccv is forced down to 1.2v to provide soft-start at the beginning of the next on-cycle. also, v cci retains its value until the beginning of the next on-cycle. when v ccv increases, it causes the buck regulator duty cycle to increase and provides soft-start. when v ccv crosses over v cci , the current control loop regains control and regulates the lamp cur- rent. v ccv is limited to 150mv above v cci for the remainder of the on-cycle. in a lamp-out condition, v cci increases the primary voltage in an attempt to maintain lamp current regula- tion. as v cci rises, v ccv rises with it until the primary voltage reaches its set limit point. at this point, v ccv stops rising and limits the primary voltage by limiting the duty cycle. because v ccv is limited to 150mv above v cci , the voltage control loop is quickly able to limit the primary voltage. without this clamping feature, the transformer voltage would overshoot to dangerous levels because v ccv would take more time to slew down from its supply rail. once the max1739/max1839 sense less than 1/6 the full-scale current through the lamp for 2 seconds, it shuts down the royer oscillator (see lamp-out detection ). see the sense resistors section for information about setting the voltage and current control loop thresholds. feed-forward control both control loops are influenced by the input voltage feed-forward (v batt ) control circuitry of the max1739/ max1839. feed-forward control instantly adjusts the buck regulator s duty cycle when it detects a change in input voltage. this provides immunity to changes in input voltage at all brightness levels. this feature makes compensation over wide input ranges easier, makes startup transients less dependent on input volt- age, and improves line regulation for short dpwm on- times. the max1739/max1839 feed-forward control is imple- mented by varying the amplitude of the buck-switch s pwm ramp amplitude. this has the effect of varying the duty cycle as a function of input voltage while maintain- ing the same v cci and v ccv . in other words, v batt feed forward has the effect of not requiring changes in error- signal voltage (v cci and v ccv ) to respond to changes in v batt . since the capacitors only need to change their voltage minimally to respond to changes in v batt , the controller s response is essentially instantaneous. transient overvoltage protection from dropout the max1739/max1839 are designed to maintain tight control of the transformer primary under all transient conditions. this includes transients from dropout, where v batt is so low that the controller loses regula- tion and reaches maximum duty cycle. backlight designs will want to choose circuit component values to minimize the transformer turns ratio in order to minimize primary-side currents and i 2 r losses. to achieve this,
max1739/max1839 ? wide brightness range ccfl backlight controllers 12 ______________________________________________________________________________________ buck enable mindac = vl? y = 1, n = 0 supply cs cs sh/sus ref bst dh lx dl1 dl2 vl batt mindac ref csav cci ccv 450mv 500mv ccv clamp ctfb 0.6v sync cs ref vl vl lamp current and dpwm control royer osc dpwm osc peak detector gnd smbus gmi gmv pk_det_clamp buck regulator pwm control pwm ramp generator crf/sda ctl/scl mode figure 2. functional diagram
max1739/max1839 ? wide brightness range ccfl backlight controllers ______________________________________________________________________________________ 13 allow the circuit to operate in dropout at extremely low battery voltages where the backlight s performance is secondary. all backlight circuit designs can undergo a transient overvoltage condition when the laptop is plugged into the ac adapter and v batt suddenly increases. the max1739/max1839 contain a unique clamp circuit on v cci . along with the feed-forward cir- cuitry, it ensures that there is not a transient transformer overvoltage when leaving dropout. the pk_det_clamp circuit limits v cci to the peaks of the buck-regulator s pwm ramp generator. as the cir- cuit reaches dropout, v cci approaches the peaks of the pwm ramp generator in order to reach maximum duty cycle. if v batt decreases further, the control loop loses regulation and v cci tries to reach its positive sup- ply rail. the clamp circuit on v cci keeps this from hap- pening, and v cci rides just above the peaks of the pwm ramp. as v batt decreases further, the feed-for- ward pwm ramp generator loses amplitude and the clamp drags v cci down with it to a voltage below where v cci would have been if the circuit was not in dropout. when vbatt is suddenly increased out of dropout, v cci is still low and maintains the drive on the transformer at the old dropout level. the circuit then slowly corrects and increases v cci to bring the circuit back into regulation. buck regulator the buck regulator uses the signals from the pwm comparator, the current-limit detection on cs, and dpwm signals to control the high-side mosfet duty cycle. the regulator uses voltage-mode pwm control and is synchronized to the royer oscillator. a falling edge on sync turns on the high-side mosfet after a 375ns minimum off-time delay. the pwm comparator or the cs current limit ends the on-cycle. interface selection table 1 lists the functionality of sh /sus, crf/sda, and ctl/scl in each of the three interface modes of the max1739/max1839. the max1739 features both an smbus digital interface and an analog interface, while the max1839 features only the analog interface. note that mode can also synchronize the dpwm frequency (see synchronizing the dpwm frequency ). dimming range brightness is controlled by either the analog interface (see analog interface ) or the smbus interface (see smbus interface ). ccfl brightness is adjusted in three ways: 1) lamp current control, where the magnitude of the average lamp current is adjusted. 2) dpwm control, where the average lamp current is pulsed to the lamp with a variable duty cycle. 3) a combination of the first two methods. in each of the three methods, a 5-bit brightness code is generated from the selected interface and is used to set the lamp current and/or dpwm duty cycle. the 5-bit brightness code defines the lamp current level with ob00000 representing minimum lamp current and ob11111 representing maximum lamp current. the average lamp current is measured across an external sense resistor (see sense resistors ). the voltage on the sense resistor is measured at csav. the brightness code adjusts the regulation voltage at csav (v csav ). the minimum average v csav is v mindac /10, and the maximum average is set by the following formula: v csav = v ref ? 31 / 320 + v mindac / 320 which is between 193.75mv and 200mv. note that if v csav does not exceed 100mv peak (which is about 32mv average) for over 2 seconds, the max1739/max1839 will assume a lamp-out condition and shut down (see lamp-out detection ). the equation relating brightness code to c sav regula- tion voltage is: v csav = v ref ? n / 320 + v mindac ? (32 - n) / 320 where n is the brightness code. to always use maximum average lamp current when using dpwm control, set v mindac to v ref . dpwm control works similar to lamp current control in that it also responds to the 5-bit brightness code. a digital interface analog interface pin mode = vl (max1739 only) mode = ref, v ctl /scl = 0 = maximum brightness mode = gnd, v ctl /scl = 0 = minimum brightness sh /sus smbus suspend logic-level shutdown control input crf/sda smbus data i/o reference input for minimum brightness reference input for maximum brightness ctl/scl smbus clock input analog control input to set brightness (range from 0 to crf/sda) table 1. interface modes
max1739/max1839 ? wide brightness range ccfl backlight controllers 14 ______________________________________________________________________________________ brightness code of ob00000 corresponds to a 9.375% dpwm duty cycle, and a brightness code of ob11111 corresponds to a 100% dpwm duty cycle. the duty cycle changes by 3.125% per step, except codes ob00000 to ob00011 all produce 9.375% (figure 3). to disable dpwm and always use 100% duty cycle, set v mindac to vl. note that with dpwm disabled, the equations above should assume v mindac = 0 instead of v mindac = vl. table 2 lists mindac s functionality, and table 3 shows some typical settings for the bright- ness adjustment. in normal operation, v mindac is set between 0 and v ref , and the max1739/max1839 use both lamp cur- rent control and dpwm control to vary the lamp bright- ness (figure 4). in this mode, lamp current control regulates the average lamp current during a dpwm on- cycle and not the overall average lamp current. analog interface and brightness code the max1739/max1839 analog interface uses an inter- nal adc with 1-bit hysteresis to generate the brightness code used to dim the lamp (see dimming range ). ctl/sda is the adc s input, and crf/scl is its refer- ence voltage. the adc can operate in either positive- scale adc mode or negative-scale adc mode. in positive-scale adc mode, the brightness code increas- es from 0 to 31 as v ctl increases from 0 to v crf . in negative-scale mode, the brightness scale decreases from 31 to 0 as v ctl increases from 0 to v crf (figure 5) . the analog interface s internal adc uses 1-bit hystere- sis to keep the lamp from flickering between two codes. v ctl s positive threshold (v ctl(th) ) is the voltage required to transition the brightness code as v ctl increases and can be calculated as follows: v ctl(th) = (n + 2) / 33 v crf (positive-scale adc mode, mode = gnd) v ctl(th) = (33 - n) / 33 v crf (negative-scale adc mode, mode = ref) where n is the current selected brightness code. v ctl s negative threshold is the voltage required to transition the brightness code as v ctl decreases and can be calculated as follows: v ctl(th) = n / 33 v crf (positive-scale adc mode, mode = gnd) v ctl(th) = (31 - n) / 33 v crf (negative-scale adc mode, mode = ref) figure 5 shows a graphic representation of the thresh- olds. crf/sda s and ctl/scl s input voltage range is 2.7v to 5.5v. mindac = vl dpwm disabled (always on 100% duty cycle). operates in lamp current control only. (use v mindac = 0 in the equations.) mindac = ref dpwm control enabled, duty cycle ranges from 9% to 100%. lamp current control is disabled (always maximum current). 0 v mindac < v ref the device uses both lamp current control and dpwm. table 2. mindac functionality 0 10 20 30 60 70 40 50 80 90 100 012 48 20 16 24 28 32 brightness code dpwm duty cycle (%) dpwm settings figure 3. dpwm settings 0 10 20 30 60 70 40 50 80 90 100 012 48 20 16 24 28 32 brightness code combined power level (%) combined power level (both dpwm and lamp control current) figure 4. combined power level
max1739/max1839 ? wide brightness range ccfl backlight controllers ______________________________________________________________________________________ 15 see digital interface for instructions on using the smbus interface. synchronizing the dpwm frequency mode has two functions: one is to select the interface mode as described in interface selection , and the other is to synchronize the dpwm chopping frequency to an external signal to prevent unwanted effects in the display screen. to synchronize the dpwm frequency, connect mode to vl, ref, or gnd through a 10k ? resistor. then con- nect a 500pf capacitor from an ac signal source to mode as shown in figure 6. the synchronization range is from 32khz to 100khz, which corresponds to a dpwm frequency range of 250hz to 781hz (128 mode pulses per dpwm cycle). high dpwm frequencies limit the dimming range. see loop compensation for more information concerning high dpwm frequencies. royer oscillator mosfet drivers the max1739/max1839 directly drive the two external mosfets used in the royer oscillator. this has many advantages over the traditional method that uses bipo- lar switching and an extra winding on the transformer. directly driving the mosfet eliminates the need for an extra winding on the transformer, which reduces cost and minimizes the size of the transformer. also, driving the switches directly improves commutation efficiency and commutation timing. using mosfets for the switches typically improves overall inverter efficiency due to lower switch drops. the royer topology works as a zero voltage crossing (zvc) detector and switches currents between the two sections of the transformer primary windings. the two windings work alternately, each generating a half wave that is transferred to the secondary to produce the full- wave sinusoidal lamp voltage and current. the max1739/max1839 detect the zero crossing through the sync pin; the threshold is set at 500mv referred to cs and has a typical delay of 50ns. the active switch- ing forces commutation very close to the zvc point and has better performance than the traditional winding- based zvc switchover. commutation can be further brightness positive- scale adc negative- scale adc smbus dac output dpwm duty cycle (%) combined power level (%) maximum brightness mode = gnd, v ctl/scl = v crf/sda mode = ref, v ctl/scl = 0 bright [4:0] = ob11111 full-scale dac output = 195.83mv 100 100 minimum brightness mode = gnd, v ctl/scl = 0, v mindac = v ref / 3 mode = ref, v ctl/scl = v crf/sda , v mindac = v ref / 3 bright [4:0] = ob00000, v mindac = v ref / 3 zero-scale dac output = v mindac / 10 93 table 3. brightness adjustment ranges (for 33:1 dimming) note: the current-level range is solely determined by the mindac-to-ref ratio and is externally set. brightness code 31 30 29 3 2 1 0 1 33 2 33 3 33 4 33 v ctl v crf (mode = gnd) v ctl v crf (mode = ref) 30 33 31 33 32 33 1 32 33 31 33 30 33 29 33 3 33 2 33 1 33 0 1 figure 5. brightness code
max1739/max1839 ? wide brightness range ccfl backlight controllers 16 ______________________________________________________________________________________ optimized using r14 and r15 as shown in figure 7. the resistor-divider can be used to force commutation as close to the zero-crossing point as possible. por and uvlo the max1739/max1839 include power-on reset (por) and undervoltage lockout (uvlo) features. the por resets all internal registers, such as dac output, fault conditions, and all smbus registers. por occurs when vl is below 1.5v. the smbus input logic thresholds are designed to meet electrical characteristic limits for vl as low as 3.5v, but the interface will continue to func- tion down to the por threshold. the uvlo threshold occurs when vl is below 4.2v (typ) and disables the buck-switch driver. low-power shutdown when the max1739/max1839 are placed in shutdown, all ic functions are turned off except the 5v linear regu- lator that powers all internal registers and the smbus interface (max1739). the smbus interface is accessi- ble in shutdown. in shutdown, the linear regulator out- put voltage drops to about 4.5v and the supply current is 6a (typ), which is the required power to maintain all internal register states. while in shutdown, lamp-out detection and buck-switch short-circuit detection latch- es are reset. the device can be placed into shutdown by either writing to the mode register (max1739 smbus mode only) or with sh /sus. lamp-out detection for safety, during a lamp-out condition, the max1739/ max1839 limit the maximum average primary-side transformer voltage (see sense resistors ) and shut down the lamp after 2s. the lamp-out detection circuitry monitors v csav and shuts down the lamp if v csav does not exceed 75mv (typ) within 2 seconds. this circuitry ignores most puls- es under 200ns. however, in some cases, a small capacitor is needed at csav to prevent noise from trip- ping the circuitry. this is especially true in noisy envi- ronments and in designs with marginal layout. ideally, the voltage at csav is a half-wave rectified sine wave. in this case, the csav lamp-out threshold is as follows: i min = i max / 6 where i min is the csav lamp out threshold, and i max is the maximum lamp current (see sense resistors ). note: the formulas assume a worst-case csav lamp-out threshold of 100mv and a maximum csav average voltage of 200mv. use mindac or limit the brightness code to prevent setting the lamp current below the csav lamp-out threshold. status1 bit sets when the lamp-out detection circuit shuts down the device. buck-switch short fault detection and protection when the buck switch (n1) fails short, there is no volt- age limiting on the transformer and the input forces excessive voltage on the transformer secondary. this figure 6. dpwm synchronization mode gnd dpwm synchronization signal 10k 500pf adc- adc+ smbus vl ref max1739 max1839 figure 7. adjusting the zvc detection sync r14 r15 r4 r5 ref ctfb lx l1 t1 gnd max1739 max1839
max1739/max1839 ? wide brightness range ccfl backlight controllers ______________________________________________________________________________________ 17 figure 8. standard application circuit increases the circuit s demand for current but may not be enough to blow the fuse. with the buck switch short- ed, the center tap rises above its regulation point, which causes the ccv amplifier s output (v ccv ) to go low. to detect this, the max1739/max1839 check that v ccv is below 1v at the end of every dpwm period. if this condition persists for over 250ms (or 64 dpwm pulses), the inverter switch commutation is stopped with either dl1 or dl2 on. with the buck switch short- ed, this will cause a short circuit with enough current to blow the fuse. if the buck switch is not shorted, then the inverter latches off as in a lamp-out condition. both buck-switch short and lamp-out detection will clear the status1 bit in the smbus interface. sta- tus1 does not clear immediately but will clear about 2 seconds after the inverter has been forced off (see digital interface ). note that once the inverter board fuse has blown, smbus communications with the part will cease since the max1739 will then be without power. applications information as shown in the standard application circuit (figure 8), the max1739/max1839 regulate the current of a 4.5w ccfl. the ic s analog voltage interface sets the lamp brightness with a minimum 20:1 power adjustment range. this circuit operates from a wide supply-voltage range of 7v to 24v. typical applications include note- book, desktop monitor, and car navigation displays. ccfl specifications to select the correct component values for the max1739/max1839 circuit, several ccfl parameters (table 4) and the minimum dc input voltage must be specified. royer oscillator components t1, c6, c7, n2a, and n2b form the royer oscillator. a royer oscillator is a resonant tank circuit that oscillates at a frequency dependent on c7, the pri- mary magnetizing inductance of t1 (lp), and the impedance seen by the t1 secondary. figure 8 shows batt v in (5v to 28v) c9 4.7 f c3 c4 c6 c7 n2b r13 n2a d5 t1 n1 d2 d1 r4 r5 c5 l1 c2 c1 vl vl dhi bst lx sync ctfb dl2 dl1 gnd cs csav ccv cci ref mindac crf/sda dimming on/off ctl/scl sh/sus max1739 max1839 mode
max1739/max1839 ? wide brightness range ccfl backlight controllers 18 ______________________________________________________________________________________ a proven application that is useful for a wide range of ccfl tubes and power ranges. table 5 shows the rec- ommended components for a 4.5w application. mosfets the max1739/max1839 require three external switches to operate: n1, n2a, and n2b. n1 is the buck switch; select a logic-level n-channel mosfet with low r dson to minimize conduction losses (100m ? , 30v typ). also select a comparable-power schottky diode for d1. n2a/n2b are the royer oscillator switches that drive the transformer primary; select a dual-logic-level n- channel mosfet with low r dson to minimize conduc- tion losses (100m ? , 30v typ). sense resistors r4 and r5 sense the transformer s primary voltage. figure 9 shows the relationship between the primary and secondary voltage. to set the maximum average secondary transformer voltage, set r5 = 10k ? , and select r5 according to the following formula: where v s is the maximum rms secondary transformer voltage (above the strike voltage), and n is the turns ratio of the transformer. rr v n s rms 45 15 1 =? ? ? ? ? ? ? . () specification symbol units description ccfl minimum strike voltage (kick-off voltage) v s v rms although ccfls typically operate at <550v rms , a higher voltage (1000v rms and up) is required initially to start the tube. the strike voltage is typically higher at cold temperatures and at the tube s end of life. this voltage is set by the combination of the maximum primary voltage (center-tap voltage limit corresponding to v ctfb = 0.6v) and the transformer (t1) turns ratio. ccfl typical operating voltage (lamp voltage) v l v rms once a ccfl has been struck, the voltage required to maintain light output falls to approximately 550v rms . short tubes may operate on as little as 250v rms . the ccfl operating voltage stays relatively constant, even as the tube s brightness is varied. ccfl maximum operating current (lamp current) i l ma rms the maximum rms ac current through a ccfl is typically 5ma rms . dc current is not allowed through ccfls. the maximum lamp current is set by the sense resistor (r13) at the maximum brightness setting. ccfl maximum frequency (lamp frequency) f l khz the maximum ac-lamp-current frequency. the max1739/ max1839 synchronize to the royer oscillator frequency set by the external components and are designed to operate between 32khz and 100khz. designation description recommended device manufacturer l1 47h, 1.1a inductor cr104-470 sumida n1 30v, 0.1 ? n-channel mosfet fdn361an fairchild n2 30v, 95m ? dual n-channel mosfet fdc6561an fairchild t1 8.7h, 180:1 transformer 5371-t001 (ciuh842 style) sumida d1 30v, 1a schottky diode crs02 toshiba d2 0.1a schottky diode bat54 fairchild d3 0.1a dual schottky diode mmbd4148se fairchild c6 22pf, 3.1kv capacitor ghm1038-sl-220j-3k murata c7 0.1f, 63v, low-dissipation capacitor smd1812 wima table 4. ccfl specifications table 5. components for the standard application circuit
max1739/max1839 ? wide brightness range ccfl backlight controllers ______________________________________________________________________________________ 19 the max1739/max1839 regulate the average current through the ccfl. the current is sensed through the sense resistor (r13) at csav. the voltage at csav is the half-wave rectified representation of the current through the lamp (figure 10). the max1739/max1839 regulate the average voltage at csav (i r13, avg ? r13) and are controlled by either the analog interface or the smbus interface. to set the maximum lamp current, determine r13 as follows: r13 = 0.4304 / i l,rms,max where i l,rms,max is the maximum rms lamp current. mindac and the wave shape influence the actual max- imum rms lamp current. use an rms current meter to make final adjustments to r13. loop compensation c cci sets the speed of the current control loop that is used during startup, maintaining lamp current regula- tion, and during transients caused by changing the lamp current setting. the standard c cci value is 0.01f. larger values limit lamp current overshoot. smaller values speed up its response to changes in the lamp current setting, but can lead to instability for extremely small values. very large values of c cci increase the delay to strike voltage in dpwm and can cause loss of regulation in the extreme case. note that very large c ccv can do the same thing. c 6 not only affects loop compensation, but it also affects the waveform shape, overall efficiency, and the maxi- mum necessary secondary transformer voltage. low val- ues of c 6 improve loop stability, especially in systems using a ccfl with a large difference between its restrike voltage and its operating voltage (characteristic of long narrow ccfls) during dpwm. a low value of c 6 also improves stability when the lamp s operating voltage drops with an increase in lamp current. however, low values of c 6 increase the maximum necessary trans- former voltage. c 7 interacts with c 6 and affects the royer frequency, royer q value, and overall efficiency. c ccv sets the speed of the voltage control loop that affects dpwm transients and operation in fault condi- tions. if dpwm is not used, the voltage control loop should only be active during fault conditions. the stan- dard value of c ccv is 3300pf. use the smallest value of c ccv necessary to set an acceptable fault transient response and not cause excessive ringing at the begin- ning of a dpwm pulse. note that the worst-case fault r4 to ctfb r5 t1 v ct l1 n p n p n s v s = v s(rms) = n ? 1.1 ? vct n = n s /n p n2b n2a 2 n v ct 2 t1 secondary voltage (pin 10?in 6) -n v ct 2 2 v ct 2 t1 primary-tap voltage (pin 2) v ct is the average dc voltage at center top d5a d5b csav r13 t1 c6 ccfl 2 i l,pk i l,rms -i l,pk i lamp i l,pk i r13, avg 2 i r13 i l, rms, max = 0.04304 r13 figure 9. transformer primary/secondary voltage relationship figure 10. current-sense waveforms
max1739/max1839 ? wide brightness range ccfl backlight controllers 20 ______________________________________________________________________________________ transient that c ccv is designed to protect against is open tube at the beginning of dpwm pulses. large c ccv values reduce transient overshoots, but can cause loss of regulation at low dpwm duty cycles by increasing the delay to strike voltage. smaller values of c ccv allow quicker dpwm startups and faster response to fault conditions. very small values of c ccv make the circuit more susceptible to ringing, and in extreme cases may cause instability. some ringing is expected between the royer oscillator and the buck inductor. some of the ringing can be suppressed by adding a capacitor in parallel with r5. this capacitor should be chosen such that: 1 / (2 ? ? r5 ? c) = ringing frequency when using high dpwm frequencies and low dpwm duty cycles, the dpwm on-time is reduced. in some cases, this causes the lamp current transient to exceed the dpwm on-time. in this case, the max1739/ max1839 lose regulation and the lamp current never reaches the lamp current set point. supply rejection while operating in this condition is degraded. if the dpwm on-time is short enough, the lamp current does not have enough time to reach the lamp-out threshold and causes a lamp-out detection. to prevent this, decrease the turn-on transient duration (by lowering c ccv ), increase the dpwm duty cycle (by limiting the brightness code), or decrease the dpwm frequency (see synchronizing the dpwm frequency ). dpwm or other chopping methods can cause audible noise from some transformers. the transformer should be carefully designed to avoid such behavior. dimming range the external components required to achieve a dim- ming range are highly dependent on the ccfl used. the standard application circuit uses a ccfl with strin- gent requirements. to achieve a 20:1 dimming range, the standard circuit drops slightly more voltage across c6 as it does across the ccfl at the full lamp current setting. this ensures good stability in that circuit with v mindac as low as 1v. to further increase the dimming range when using this ccfl, c6 must be increased, which increases the maximum secondary transformer voltage and requires a transformer with a higher volt- age rating. other components (such as the primary transformer inductance and c 7 ) may also need to be adjusted to maintain good waveforms, royer efficiency, and the desired royer frequency. other components the high-side mosfet driver is powered by the exter- nal boosting circuit formed by c5 and d2. connect bst through a signal-level schottky diode to vl, and bypass it to lx with a 0.1f ceramic capacitor. this cir- cuit delivers the necessary power to drive n1 as shown in figure 8. if a higher gate capacitance mosfet is used, the size of the bypass capacitor must be increased. the current need at bst is as follows: i bst = 1ma d + q t ? f where d is the buck controller duty cycle (98% max), q t is the mosfet total gate charge, and f is twice the royer oscillator frequency. the maximum current through d2 (i d ) is: i d = i bst / (1 - d) d5a and d5b are used to generate the current-sense voltage across r13. the current through these diodes is the lamp current; use a dual-series signal-level diode. bypassing and board layout connect c4 from vl to gnd as close as possible with dedicated traces that are not shared with other signal paths. the ground lines should terminate at the gnd end of c4: quiet ground, power ground, and lamp cur- rent-sense ground. quiet ground is used for ref, ccv, r5, and mindac (if a resistor-divider is used). the power ground goes from the ground of c4 directly to the ground side of c9. power ground should also sup- ply the return path for d1, n2, and the buck current- sense resistor (from cs to gnd, if used). the ground path for r13 should be separate to ensure that it does not corrupt quiet ground and it is not affected by dc drops in the power ground. refer to the max1739 ev kit for an example of good layout. digital interface (max1739) with mode connected to vl, the crf/sda and ctl/scl pins no longer behave as analog inputs; instead, they function as smbus-compatible 2-wire dig- ital interfaces. crf/sda is the bidirectional data line, and ctl/scl is the clock line of the 2-wire interfaces corresponding, respectively, to the smbdata and smbclk lines of the smbus. the max1739 uses the write-byte, read-byte, and receive-byte protocols (figure 11). the smbus protocols are documented in system management bus specification v1.08 and are available at www.sbs-forum.org. the max1739 is a slave-only device and responds to the 7-bit address 0b0101101 (i.e., with the r w bit clear indicating a write, this corresponds to 0x5a). the max1739 has three functional registers: a 5-bit bright- ness register (bright4 bright0), a 3-bit shutdown mode register (shmd2 shmd0), and a 2-bit status register (status1 status0). in addition, the device
max1739/max1839 ? wide brightness range ccfl backlight controllers ______________________________________________________________________________________ 21 has three identification (id) registers: an 8-bit chip id register, an 8-bit chip revision register, and an 8-bit manufacturer id register. the crf/sda and ctl/scl pins have schmidt-trig- gered inputs that can accommodate slow edges; how- ever, the rising and falling edges should still be faster than 1s and 300ns, respectively. communication starts with the master signaling the beginning of a transmission with a start condition, which is a high-to-low transition on crf/sda while ctl/scl is high. when the master has finished com- municating with the slave, the master issues a stop condition (p), which is a low-to-high transition on crf/sda while ctl/scl is high (figures 10, 11). the bus is then free for another transmission. figures 12 and 13 show the timing diagram for signals on the 2-wire interface. the address byte, command byte, and data byte are transmitted between the start and stop conditions. the crf/sda state is allowed to change only while ctl/scl is low, except for the start and stop conditions. data is transmitted in 8- bit words and is sampled on the rising edge of ctl/scl. nine clock cycles are required to transfer each byte in or out of the max1739 since either the master or the slave acknowledges the receipt of the correct byte during the ninth clock. if the max1739 receives its correct slave address followed by r w = 0, it expects to receive 1 or 2 bytes of information (depending on the protocol). if the device detects a start or stop condition prior to clock- ing in the bytes of data, it considers this an error condition and disregards all of the data. if the transmission is com- pleted correctly, the registers are updated immediately after a stop (or restart) condition. if the max1739 receives its correct slave address followed by r w = 1, it expects to clock out the register data selected by the pre- vious command byte. smbus commands the max1739 registers are accessible through several different redundant commands (i.e., the command byte in the read-byte and write-byte protocols), which can 1b ack 1b 7 bits address ack 1b wr 8 bits data 1b ack p 8 bits s command write-byte format receive-byte format slave address command byte: selects which register you are writing to data byte: data goes into the register set by the command byte 1b ack 1b 7 bits address ack 1b wr s 1b ack 8 bits data 7 bits address 1b rd 1b 8 bits /// p s command slave address slave address command byte: sends command with no data; usually used for one- shot command command byte: selects which register you are reading from slave address: repeated due to change in data- flow direction data byte: reads from the register set by the command byte 1b ack 7 bits address 1b rd 8 bits data 1b /// p s data byte: reads data from the register commanded by the last read-byte or write-byte transmission; also used for smbus alert response return address s = start condition shaded = slave transmission wr = write = 0 p = stop condition ack= acknowledged = 0 rd = read =1 /// = not acknowledged = 1 figure 11. smbus protocols 1b ack 7 bits address 1b wr 8 bits command 1b ack p s send-byte format read-byte format
max1739/max1839 ? wide brightness range ccfl backlight controllers 22 ______________________________________________________________________________________ be used to read or write the brightness, shmd, status, or id registers. table 6 summarizes the command byte s register assignments, as well as each register s power-on state. the max1739 also supports the receive-byte protocol for quicker data transfers. this protocol accesses the register configuration pointed to by the last command byte. immediately after power-up, the data byte returned by the receive-byte protocol is the contents of the brightness register, left justified (i.e., bright4 will be in the msb position of the data byte) with the remaining bits containing a 1, status1, and status0. this gives the same result as using the read-byte proto- col with a 0b10xxxxxx (0x80) command. use caution with shorter protocols in multimaster systems since a second master could overwrite the command byte with- out informing the first master. during shutdown, the ser- ial interface remains fully functional. the part also supports limited read/write-word protocol. read-word works similar to read-byte except the second byte returned is 0xff. write-word also works similar to write- byte. the second data byte is acknowledged and updated after the first data byte is acknowledged and updated. smbclk ab cd e fg h i j k smbdata t su:sta t hd:sta t low t high t su:dat t hd:dat t hd:dat t su:sto t buf a = start condition b = msb of address clocked into slave c = lsb of address clocked into slave d = r/w bit clocked into slave e = slave pulls smbdata line low l m f = acknowledge bit clocked into master g = msb of data clocked into slave h = lsb of data clocked into slave i = slave pulls smbdata line low j = acknowledge clocked into master k = acknowledge clock pulse l = stop condition, data executed by slave m = new start condition figure 12. smbus write timing smbclk a = start condition b = msb of address clocked into slave c = lsb of address clocked into slave d = r/w bit clocked into slave ab cd e fg h i j smbdata t su:sta t hd:sta t low t high t su:dat t hd:dat t su:dat t su:sto t buf k e = slave pulls smbdata line low f = acknowledge bit clocked into master g = msb of data clocked into master h = lsb of data clocked into master i = acknowledge clock pulse j = stop condition k = new start condition figure 13. smbus read timing
max1739/max1839 ? wide brightness range ccfl backlight controllers ______________________________________________________________________________________ 23 brightness register [bright4?right0] (por = 0b10111) the 5-bit brightness register corresponds with the 5-bit brightness code used in the dimming control (see dimming range ). bright4 bright0 = 0b00000 sets minimum brightness, and bright4 bright0 = 0b11111 sets maximum brightness. the smbus inter- face does not control whether the device regulates the current by analog dimming, dpwm dimming, or both; this is done by mindac (table 2). shutdown-mode register [shmd2?hmd0] (por = 0b001) the 3-bit shutdown-mode register configures the oper- ation of the device when the sh /sus pin is toggled as described in table 7. the shutdown-mode register can also be used to shut off directly the ccfl, regardless of the sh /sus state (table 8). data register bit assignment r or w protocol command byte* por state bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) read and write 0x01 0b0xxx xx01 0x17 0 0 0 bright4 (msb) bright3 bright2 bright1 bright0 (lsb) read and write 0x02 0b0xxx xx10 0xf9 status1 status0 1 1 1 shmd2 shmd1 shmd0 read only 0x03 0b0xxx xx11 0x96 chipid7 1 chipid6 0 chipid5 0 chipid4 1 chipid3 0 chipid2 1 chipid1 1 chipid0 0 read only 0x04 0b0xxx xx00 0x00 chiprev7 0 chiprev6 0 chiprev5 0 chiprev4 0 chiprev3 0 chiprev2 0 chiprev1 0 chiprev0 0 read and write 0x40 0b10xx xxxx 0xbf bright4 (msb) bright3 bright2 bright1 bright0 (lsb) 1 status1 status0 read only 0xfe 0b11xx xxx0 0x4d mfgid7 0 mfgid6 1 mfgid5 0 mfgid4 0 mfgid3 1 mfgid2 1 mfgid1 0 mfgid0 1 read only 0xff 0b11xx xxx1 0x96 chipid7 1 chipid6 0 chipid5 0 chipid4 1 chipid3 0 chipid2 1 chipid1 1 chipid0 0 *the hexadecimal command byte shown is recommended for maximum forward compatibility with future maxim products. table 6. commands description
max1739/max1839 ? wide brightness range ccfl backlight controllers 24 ______________________________________________________________________________________ status register [status1?tatus0] (por = 0b11) the status register returns information on fault condi- tions. if a lamp is not connected to the secondary of the transformer, the max1739 will detect that the lamp cur- rent has not exceeded the csav detection threshold and after 2 seconds will clear the status1 bit (see lamp-out detection ). the status1 bit is latched; i.e., it will remain 0 even if the lamp-out condition goes away. when status1 = 0, the lamp is forced off. sta- tus0 reports 1 as long as no overcurrent conditions are detected. if an overcurrent condition is detected in any given dpwm period, status0 is cleared for the duration of the following dpwm period. if an overcur- rent condition is not detected in any given dpwm peri- od, status0 is set for the duration of the following dig- ital dpwm period. forcing the ccfl lamp off by entering shutdown, writing to the mode register, or by toggling sh /sus sets status1. id registers the id registers return information on the manufacturer, the chip id, and the chip revision number. the max1739 is the first-generation advanced ccfl con- troller, and its chiprev is 0x00. reading from the mfgid register returns 0x4d, which is the ascii code for m (for maxim); the chipid register returns 0x96. writing to these registers has no effect. bit name por state description 2 shmd2 0 shmd2 = 1 forces the lamp off and sets status1. shmd2 = 0 allows the lamp to operate, though it may still be shut down by the sh/ sus pin (depending on the state of shmd1 and shmd0). 1 shmd1 0 when sh /sus = 0, this bit has no effect. sh /sus = 1 and shmd1 = 1 forces the lamp off and sets status1. sh /sus = 1 and shmd1 = 0 allow the lamp to operate, though it may still be shut down by the shmd2 bit. 0 shmd0 1 when sh /sus = 1, this bit has no effect. sh /sus = 0 and shmd0 = 1 forces the lamp off and sets status1. sh /sus = 0 and shmd0 = 0 allows the lamp to operate, though it may still be shut down by the shmd2 bit. table 7. shmd register bit descriptions sh /sus shmd2 shmd1 shmd0 operating mode 0 0 x 0 operate 0 0 x 1 shutdown, status1 set 1 0 0 x operate 1 0 1 x shutdown, status1 set x 1 x x shutdown, status1 set table 8. sh /sus and shmd register truth table bit name por state description 1 status1 1 status1 = 0 means that a lamp-out condition has been detected. the status1 bit stays clear even after the lamp-out condition has gone away. the only way to set status1 is to shut off the lamp by programming the mode register or by toggling sh /sus. 0 status0 1 status0 = 0 means that an overcurrent condition was detected during the previous digital pwm period. status0 = 1 means that no overcurrent condition was detected during the previous digital pwm period. table 9. status register bit descriptions (read only/writes have no effect) x = don t care
max1739/max1839 ? wide brightness range ccfl backlight controllers ______________________________________________________________________________________ 25 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 batt dh lx bst ccv cci mindac ref top view vl gnd cs dl1 mode ctl crf sh 12 11 9 10 dl2 sync ctfb csav max1839 qsop pin configurations (continued) chip information transistor count: 7194
max1739/max1839 ? wide brightness range ccfl backlight controllers qsop.eps package information maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 26 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2001 maxim integrated products printed usa is a registered trademark of maxim integrated products.

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